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DATA SHEET
MOS INTEGRATED CIRCUIT
PD4416001
16M-BIT CMOS FAST SRAM 16M-WORD BY 1-BIT
Description
The PD4416001 is a high speed, low power, 16,777,216 bits (16,777,216 words by 1 bits) CMOS static RAM. Operating supply voltage is 3.3 V 0.3 V. The PD4416001 is packaged in a 54-PIN PLASTIC TSOP (II).
Features
* 16,777,216 words by 1 bits * Fast access time : 15, 17 ns (MAX.) * Output Enable input for easy application
Ordering Information
Part number Package Supply voltage V Access time ns (MAX.) 15 17 Supply current mA (MAX.) At operating 165 160 At standby 10
* *
PD4416001G5-A15-9JF PD4416001G5-A17-9JF
54-PIN PLASTIC TSOP (II) (10.16 mm (400))
3.3 0.3
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. M14077EJ3V0DS00 (3rd edition) Date Published December 2000 NS CP(K) Printed in Japan
The mark * shows major revised points.
(c)
1999
PD4416001
Pin Configuration (Marking Side)
/xxx indicates active low signal.
54-PIN PLASTIC TSOP (II) (10.16 mm (400)) [PD4416001G5-xxx-9JF] - -
NC VCC NC NC GND NC A0 A1 A2 A3 A4 A5 /CS VCC /WE A6 A7 A8 A9 A10 A11 DIN VCC NC NC GND NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
NC GND NC NC VCC NC A23 A22 A21 A20 A19 A18 /OE GND IC A17 A16 A15 A14 A13 A12 DOUT GND NC NC VCC NC
A0 - A23 DIN DOUT /CS /WE /OE VCC GND NC IC
: Address Inputs : Data Input : Data Output : Chip Select : Write Enable : Output Enable : Power supply : Ground : No connection : Internal connection
Note
Note Leave this pin connect to GND.
Remark Refer to Package Drawing for 1-pin index mark.
2
Data Sheet M14077EJ3V0DS
PD4416001
Block Diagram
VCC GND A0 A23
Address buffer
Row decoder
Memory cell array 16,777,216 bits
DIN DOUT
Input data controller
Sense / Switch Column decoder
Output data controller
Address buffer
/CS
/WE /OE
Truth Table
/CS H L L L /OE x L x H /WE x H L H Mode Not selected Read Write Output disable I/O High impedance DOUT DIN High impedance Supply current ISB ICC
Remark x : Don't care
Data Sheet M14077EJ3V0DS
3
PD4416001
Electrical Specifications
Absolute Maximum Ratings
Parameter Symbol VCC VT TA Tstg Condition -0.5 -0.5 Rating
Note Note
Unit V V C C
* *
Supply voltage Input / Output voltage Operating ambient temperature Storage temperature
to +4.0 to +4.0
0 to 70 -55 to +125
Note -2.0 V (MIN.) (pulse width : 2 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions
Parameter Supply voltage High level input voltage Low level input voltage Operating ambient temperature Symbol VCC VIH VIL TA Condition MIN. 3.0 2.0 -0.3 Note 0 TYP. 3.3 MAX. 3.6 VCC + 0.3 +0.8 70 Unit V V V C
Note -2.0 V (MIN.) (pulse width : 2 ns) DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter Input leakage current Output leakage current Symbol ILI ILO VIN = 0 V to VCC VOUT = 0 V to VCC, /CS = VIH or /OE = VIH or /WE = VIL Test condition MIN. -2 -2 TYP. MAX. +2 +2 Unit
A A
* *
Operating supply current
ICC
/CS = VIL, IOUT = 0 mA, Minimum cycle time
Cycle time : 15 ns Cycle time : 17 ns
165 160 80 10
mA
Standby supply current
ISB ISB1
/CS = VIH, VIN = VIH or VIL, Minimum cycle time /CS VCC - 0.2 V, VIN 0.2 V or VCC - 0.2 V VIN
mA
High level output voltage Low level output voltage
VOH VOL
IOH = -4.0 mA IOL = +8.0 mA
2.4 0.4
V V
Remark
VIN : Input voltage, VOUT : Output voltage
Capacitance (TA = 25 C, f = 1 MHz)
Parameter Input capacitance Input / Output capacitance Symbol CIN COUT VIN = 0 V VOUT = 0 V Test condition MIN. TYP. MAX. 6 8 Unit pF pF
Remarks 1. VIN : Input voltage, VOUT : Output voltage 2. These parameters are periodically sampled and not 100% tested.
4
Data Sheet M14077EJ3V0DS
PD4416001
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions LVTTL Interface Input Waveform (Rise and Fall Time 3 ns)
3.0 V 1.5 V GND Test Points 1.5 V
Output Waveform
1.5 V
Test Points
1.5 V
Output Load
AC characteristics directed with the note should be measured with the output load shown in Figure 1 or Figure 2. Figure 1 (for tAA, tACS, tOE, tOH)
VTT = +1.5 V
Figure 2 (for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, tOW)
+3.3 V
50 ZO = 50 DOUT (Output) 30 pF CL DOUT (Output) 351
317
5 pF CL
Remark .
CL includes capacitances of the probe and jig, and stray capacitances.
Data Sheet M14077EJ3V0DS
5
PD4416001
Read Cycle
Parameter Symbol MIN. Read cycle time Address access time /CS access time /OE access time Output hold from address change /CS to output in low impedance /OE to output in low impedance /CS to output in high impedance /OE to output hold in high impedance tRC tAA tACS tOE tOH tCLZ tOLZ tCHZ tOHZ 3 3 0 7 7 15 15 15 7 3 3 0 8 8 -A15 MAX. MIN. 17 17 17 8 -A17 MAX. ns ns ns ns ns ns ns ns ns 2, 3 1 Unit Notes
Notes 1. See the output load shown in Figure 1. 2. Transition is measured at 200 mV from steady-state voltage with the output load shown in Figure 2. 3. These parameters are periodically sampled and not 100% tested. Read Cycle Timing Chart 1 (Address Access)
tRC Address (Input) tAA tOH DOUT (Output) Previous data output Data output
Remarks 1. In read cycle, /WE should be fixed to high level. 2. /CS = /OE = VIL Read Cycle Timing Chart 2 (/CS Access)
tRC Address (Input) tAA tACS /CS (Input) tCLZ /OE (Input) tOE tOLZ DOUT (Output) High impedance Data output High impedance tOHZ tCHZ
Caution Remark 6
Address valid prior to or coincident with /CS low level input. In read cycle, /WE should be fixed to high level.
Data Sheet M14077EJ3V0DS
PD4416001
Write Cycle
Parameter Symbol MIN. Write cycle time /CS to end of write Address valid to end of write Write pulse width Data valid to end of write Data hold time Address setup time Write recovery time /WE to output in high impedance Output active from end of write tWC tCW tAW tWP tDW tDH tAS tWR tWHZ tOW 3 15 10 10 10 7 0 0 1 7 3 -A15 MAX. MIN. 17 11 11 11 8 0 0 1 8 -A17 MAX. ns ns ns ns ns ns ns ns ns ns 1, 2 Unit Notes
Notes 1. Transition is measured at 200 mV from steady-state voltage with the output load shown in Figure 2. 2. These parameters are periodically sampled and not 100% tested. Write Cycle Timing Chart 1 (/WE Controlled)
tWC Address (Input) tCW /CS (Input) tAW tAS /WE (Input) tCLZ DIN (Input) tOH DOUT (Output) tAA tWHZ tWP tWR
tACS tDW Data in tOW High impedance tDH
Cautions 1. /CS or /WE should be fixed to high level during address transition.
*
2. Do not input data to the I/O pins while they are in the output state.
Remarks 1. Write operation is done during the overlap time of a low level /CS, a low level /WE. 2. During tWHZ, DOUT pins are in the output state, therefore the input signals of opposite phase to the output must not be applied. 3. When /WE is at low level, the DOUT pins are always high impedance. When /WE is at high level, read operation is executed. Therefore /OE should be at high level to make the DOUT pins high impedance.
Data Sheet M14077EJ3V0DS
7
PD4416001
Write Cycle Timing Chart 2 (/CS Controlled)
tWC Address (Input)
tAS /CS (Input) tAW tWP /WE (Input)
tCW
tWR
tDW DIN (Input) Data in
tDH
High impedance DOUT (Input)
Cautions 1. /CS or /WE should be fixed to high level during address transition.
*
Remark
2. Do not input data to the I/O pins while they are in the output state.
Write operation is done during the overlap time of a low level /CS and a low level /WE.
8
Data Sheet M14077EJ3V0DS
PD4416001
Package Drawing
54-PIN PLASTIC TSOP (II) (10.16 mm (400))
54 28
detail of lead end F
P E 1 A H G I S L C D M
M
27
J
N
S
B
K
NOTES 1. Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. 2. Dimension "A" does not include mold fiash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side.
ITEM A B C D E F G H I J K L M N P
MILLIMETERS 22.220.05 0.91 MAX. 0.80 (T.P.) 0.32+0.08 -0.07 0.100.05 1.10.1 1.00 11.760.20 10.160.10 0.800.20 0.145+0.025 -0.015 0.500.10 0.13 0.10 3+7 -3 S54G5-80-9JF-2
Data Sheet M14077EJ3V0DS
9
PD4416001
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the PD4416001. Type of Surface Mount Device
PD4416001 : 54-PIN PLASTIC TSOP (II) (10.16 mm (400))
10
Data Sheet M14077EJ3V0DS
PD4416001
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet M14077EJ3V0DS
11
PD4416001
* The information in this document is current as of December, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
M8E 00. 4

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